Document Information click to expand document information Description: ksznl. Original Title ksznl. Did you find this document useful? Is this content inappropriate? Report this Document. Description: ksznl. Flag for inappropriate content. Download now. Save Save ksznl For Later. Original Title: ksznl. Related titles. Carousel Previous Carousel Next. Jump to Page. Search inside document. Contact factory for lead time. July M July 11 M Note: 1.
July 12 M When the input exceeds the squelch limit, the PLL locks onto the incoming July 13 M July 14 M Yes Link Mode Set Figure 1. It provides a common interface between physical layer and MAC layer devices, and has the following key characteristics: Supports 10Mbps and Mbps data rates. Provides independent 4-bit wide nibble transmit and receive data paths. Contains two distinct groups of signals: one for transmission and the other for reception.
July 16 M July 17 M Provides independent 2-bit wide di-bit transmit and receive data paths. July 18 M July 19 M Figure 4. Figure 6. Table 5. Default Register 0h Basic Control 0. This bit is ignored if auto-negotiation is enabled register 0. This bit is self-cleared after a 1 is written to it. July 24 M July 30 M July 31 M July 32 M Figure Reset Timing Parameter Description Min Max Units tsr Stable supply voltage to reset high 10 ms tcs Configuration setup time ns tch Configuration hold time ns trc Reset to strap-in pin output ns Table July 41 M Recommended Reset Circuit The following reset circuit is recommended for applications where reset is driven by another device e.
July 42 M Inter-winding capacitance max. July 45 M Documents Similar To ksznl. Carlos Bonatto. Tag Removal is enabled by bit [1] of registers 16, 32 and 48 for ports 1, 2 and 3, respectively. At the egress port, tagged packets will have their The CRC is recalculated for both tag insertion and tag removal.
If the ingress packet's priority field has a higher priority value than the default tag's priority field of the ingress port, the packet's priority field is replaced with the default tag's priority field. When the most significant 6 bits of the ToS field are fully decoded, the resultant of the 64 possibilities is compared with the corresponding bits in the DSCP register to determine priority. January 27, 35 Revision 1. The other ports port 1 and port 2 can be configured in one of the five spanning tree states via "transmit enable", "receive enable" and "learning disable" register settings in registers 18 and 34 for ports 1 and 2, respectively.
The following table shows the port setting and software actions taken for each of the five spanning tree states. Disable State Port Setting Software Action The port should not forward or "transmit The processor should not send any packets to the port. The switch may still receive any packets.
Address learning is disabled on the port in this state. Learning is The processor should not send any packets to the port s in this state. The disabled. Software Action Learning is disabled. Only packets to and from the receive enable The processor may send packets to the port s in this state. See "Tail processor are forwarded. Address learning is disabled on the port in this Learning is enabled.
The "overriding" bit should enabled. Address learning is enabled on the port in this state. The processor can learning send packets to the port s in this state. See "Tail Tagging Mode" for details. Table Spanning Tree States January 27, 36 Revision 1. Discarding state: the state includs three states of the disable, blocking and listening of STP. The switch may still send specific packets to the processor packets that match some entries in the static table with "overriding bit" set and the processor should discard those packets.
Note: processor is connected to port 3 via MII interface. Ports in Learning states learn MAC addresses, but do not forward user traffic. Learning state: only packets to and from the processor are forwarded. Learning is enabled. The "overriding" bit should be set so that the switch will forward those specific packets to the processor.
The processor may send packets to the port s in this state, see "Tail Tagging Mode" section for details. Ports in Forwarding states fully participate in both data forwarding and MAC learning. Forwarding state: packets are forwarded and received normally. Tail Tagging Mode The Tail Tag is only seen and used by the port 3 interface, which should be connected to a processor.
It is an effective way to retrieve the ingress port information for spanning tree protocol IGMP snooping and other applications. Bit 3 and bit 2 are used for the priority setting of the ingress frame in port 3.
Other bits are not used. The Tail Tag feature is enable by setting register 3 bit 6. Figure 7. Enable the tail tag mode, the host will know the IGMP packet received port from tail tag bits [0] and can send back the response IGMP packet to this subscribed port by setting the bits [1,0] in the tail tag.
Enable "Tail tag mode" by setting Register 3 bit 6. The tail tag will be removed automatically when the IGMP packet is sent out from the subscribed port. For example, port 1 is programmed to be "receive sniff" and port 3 is programmed to be the "sniffer port". A packet received on port 1 is destined to port 2 after the internal lookup.
For example, port 1 is programmed to be "transmit sniff" and port 3 is programmed to be the "sniffer port". A packet received on port 2 is destined to port 1 after the internal lookup. For example, port 1 is programmed to be "receive sniff", port 2 is programmed to be "transmit sniff", and port 3 is programmed to be the "sniffer port". Multiple ports can be selected as "receive sniff" or "transmit sniff".
In addition, any port can be selected as the "sniffer port". All these per port features can be selected through registers 17, 33 and 49 for ports 1, 2 and 3, respectively. The rate limit is independently on the "receive side" and on the "transmit side" on a per port basis. On the receive side, the data receive rate for each priority at each port can be limited by setting up Ingress Rate Control Registers.
On the transmit side, the data transmit rate for each priority queue at each port can be limited by setting up Egress Rate Control Registers. Packets are dropped at the ingress port when the data rate exceeds the specified rate limit.
For egress rate limiting, the Leaky Bucket algorithm is applied to each output priority queue for shaping output traffic. Inter frame gap is stretched on a per frame base to generate smooth, non-burst egress traffic.
The throughput of each output priority queue is limited by the egress rate specified. If any egress queue receives more traffic than the specified egress rate throughput, packets may be accumulated in the output queue and packet memory. After the memory of the queue or the port is used up, packet dropping or flow control will be triggered. To reduce congestion, it is a good practice to make sure the egress bandwidth exceeds the ingress bandwidth. This option is enabled and configured in register This function is useful in preventing the broadcast of unicast packets that could degrade the quality of the port in applications such as voice over Internet Protocol VoIP.
Some default settings are configured via strap- in pin options. January 27, 39 Revision 1. One is for read; the other is for write. Some of the configuration settings, such as "Aging enable", "Auto Negotiation Enable", "Force Speed" and "Power down" can be programmed after the switch has been started. January 27, 40 Revision 1. The tables and counters are indirectly accessed via registers to SPI Connections 2.
January 27, 41 Revision 1. The loopback is limited to few package a time for diagnosis purpose and can't support large traffic. The loopback path starts at the "Originating. Bit [0] of registers 29 and 45 is used to enable far-end loopback for ports 1 and 2, respectively. Alternatively, the MII Management register 0, bit [14] can be used to enable far-end loopback. The far-end loopback path is illustrated in Figure January 27, Figure Far-End Loopback Path Revision 1.
Bit [1] of registers 26 and 42 is used to enable near-end loopback for ports 1 and 2, respectively. Alternatively, the MII Management register 31, bit [1] can be used to enable near-end loopback. The near-end loopback paths are illustrated in Figure Figure The latter three interfaces use a different mapping mechanism than the MIIM interface.
After VCT Reg. It's approximately Reg. January 27, 49 Revision 1. Used solely for 0 Frames debugging purposes. Works in conjunction with sniffer mode only. This is not an IEEE standard. In this mode, if a flow control port and a non-flow control port talk to the same destination port, packets from Flow Control the non-flow control port may be dropped. This may not be "fair" to the flow control port. Log In New customer? Start here. Order History. Product Category: IC Chips.
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